ReSNN-DCT: Metodologia para redução de Rede Neural Spiking utilizando Transformada de Cossenos Discreta e Emparelhamento Elegante

Abstract

In recent years, the use of artificial neural network applications to perform object classification and event prediction has increased, mainly from research on deep learning techniques performed on hardware such as GPU and FPGA. Interest in the use of neural networks extends to embedded systems due to the development of applications in smart mobile devices, such as cell phones, drones, autonomous cars and industrial robots. But when it comes to embedded systems, hardware limits must be observed, such as memory and power consumption, as they significantly impact the processing of a deep neural network. In this work, a research was carried out on the state of the art of artificial neural network architectures, implemented in hardware, observing the limiting aspects such as performance, scalability or energy efficiency. From the study carried out, a methodology is proposed that allows to reduce a spiking neural network (SNN), applying the discrete cosine transform (DCT) and elegant pairing. The Izhikevich model was used as a basis for the spiking neural network architecture. The simulation results demonstrate the effectiveness of the methodology, showing the feasibility of reducing synapses, applying the DCT transform, and reducing neurons in the intermediate layers, using the elegant pairing technique of coefficients, and maintaining the accuracy of the spiking neural network. The results also demonstrate the contribution of the proposed methodology to the scalability of the neural network, with the increase in the storage capacity of the coefficients of the SNN layers.