Circuito de leitura de ISFET melhorado aplicável à leitura de PH: caracterização e comparação

Abstract

This work presents the project at the level of BSIM3V3 simulations of a conditioning circuit topology both in the integrated version (polysilicon metal-4 technology - 0.35µm CMOS) and discrete for reading ISFET sensors (Ion Sensitive Field Effect Transistor). The conditioning topology developed has some advantages over traditional topologies that are mostly CVCC (Constant Voltage and Constant Current) in three aspects: higher than conventional sensitivity (201.736mV / pH x 59mV / pH), linearity very close to 1. In addition to reading pH in the entire 3 to 12 range with a sensitivity of 201.736mV / pH, this circuit also offers an adjustment form that allows its readings to be made by ranges, where adjustments must be made to the dimensions of transistors N and P in the manufacturing stage (integrated version) and apply different voltage values to your Reference Electrode so that it is possible to read the pH with an even higher sensitivity than the conventional one with the same topology, but sized differently, making it possible to reach the sensitivity of 480mV / pH. We can then read three interspersed pH ranges, for example: range 1 - pH 3 to 7; range 2 - pH 6 to 10; ranges 3 -8 to 12. In the discrete version, the same can be done through the polarization resistors (RP and RN) of the circuit, both for reading the pH range 3 to 12 and for reading by ranges (the same ranges 1, 2 and 3). For that, one can use three circuits applied to an ISFET matrix, each with a different Reference Electrode voltage or just one circuit applied to an ISFET with that same micro controlled voltage. Output noise analysis, Signal-to-Noise ratio and Monte Carlo simulations were carried out in order to demonstrate the robustness of the circuit to noise and variations intrinsic to the components of the topology. Results show that the circuit, both in its integrated and discrete version, presents very satisfactory results to the desired applications with low noise rate and robustness to variations in the two versions presented (integrated and discrete). It was also proven that its operation is similar in both versions of the circuit, validating the topology itself.