Metodologia de reconfiguração de hardware utilizando o sinal de TV Digital

Abstract

This PhD thesis presents a novel hardware reconfiguration methodology, which uses the digital TV broadcast signal for reconfiguring hardware modules in digital TV receivers. The proposed methodology allows hardware cores to be signaled, during the transport stream generation step, transmitted and then reassembled. At the receiver, the recovered cores are then used to reconfigure reprogrammable field programmable gate array (FPGA) devices, which are integrated into each receiver unit. Besides, content signaling allows receivers to choose between FPGA cores synthesized for different manufacturers, which enables receivers to select broadcast hardware cores related to the employed FPGA models. The results of the performed experiments, which were carried out during the development of this work, consist in a proof of concept and show the technical feasibility of this methodology, regarding reconfiguration of pre-synthesized hardware cores through the digital TV environment. Receiver manufacturers could benefit from this methodology for developing reconfigurable architectures, which would allow the incorporation of technological advances into receiver hardware and provide better control regarding product life cycle. As a result, future revisions of DTV standards could occur without the need for device replacement.